Regulating control transfers for execute-only code execution

An apparatus comprising a processor, wherein the processor is configured to:

• detect a first control transfer operation;
• determine that a destination of the first control transfer operation is within code stored in execute-only memory;
• generate a fault if the destination of the first control transfer operation is an invalid entry point into the code stored in execute-only memory;
• detect a second control transfer operation while executing the code stored in execute-only memory;
• and
• abort execution of the code stored in execute-only memory if the second control transfer operation is detected at an invalid exit point in the code.

A method, comprising:

• detecting a first control transfer operation;
• determining that a destination of the first control transfer operation is within code stored in execute-only memory;
• generating a fault if the destination of the first control transfer operation is an invalid entry point into the code stored in execute-only memory;
• detecting a second control transfer operation while executing the code stored in execute-only memory;
• and
• aborting execution of the code stored in execute-only memory if the second control transfer operation is detected at an invalid exit point in the code.