Hierarchically aware interior pinning for large synthesis blocks
AssigneeInternational Business Machines Corporation
InventorsMatthew D. Affeldt, Christopher J. Berry, Randall J. Darden, Shyam Ramji, Eddy St. Juste
Life of this patent
Estimating the term…
Abstract
A system and a computer implemented method for interior pinning in a macro block of an integrated circuit are provided. The method includes receiving child level information of the macro block including at least a location of a logic leaflet, receiving parent level information including at least edge direction information for pin connection and routing resource values of each slot of the macro block at each metal layer, and selecting a pin location based on the child level information and the parent level information.
Claims20
A computer implemented method for improving interior pinning in a macro block of an integrated circuit, the method comprising:
- receiving, by a computer child level information of the macro block including at least a location of a logic leaflet in the integrated circuit;
- receiving, by the computer, parent level information including at least edge direction information for pin connection and routing resource values of each slot of the macro block at each metal layer in the integrated circuit, wherein the logic leaflet defines a connecting point for a pin in the integrated circuit;
- and
- selecting, by the computer, a pin location for the pin in the integrated circuit based on the child level information and the parent level information, which comprises determining an ideal pin placement, wherein the pin location is associated with the ideal pin placement.
A system for improving interior pinning in a macro block of an integrated circuit, the system comprising:
- a memory having computer readable instructions;
- and
- a processor configured to execute the computer readable instructions, the computer readable instructions comprising:
- receiving, by the processor, child level information of the macro block including at least a location of a logic leaflet in the integrated circuit;
- receiving, by the processor, parent level information including at least edge direction information for pin connection and routing resource values of each slot of the macro block at each metal layer in the integrated circuit, wherein the logic leaflet defines a connecting point for a pin in the integrated circuit;
- and
- selecting a pin location for the pin in the integrated circuit based on the child level information and the parent level information.
A computer program product for improving interior pinning in a macro block of an integrated circuit, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:
- receive, by the processor, child level information of the macro block including at least a location of a logic leaflet in the integrated circuit;
- receive, by the processor, child parent level information including at least edge direction information for pin connection and routing resource values of each slot of the macro block at each metal layer in the integrated circuit, wherein the logic leaflet defines a connecting point for a pin in the integrated circuit;
- and
- select, by the processor, a pin location for the pin in the integrated circuit based on the child level information and the parent level information.
Dependencies are inferred from the claim text.