US 2018/0004882 A1 · DUMMY FIN CELL PLACEMENT IN AN INTEGRATED CIRCUIT LAYOUT

Abstract

In a method of forming an integrated circuit (IC) layout, an empty region in the IC layout is identified by a processor circuit, wherein the empty region is a region of the IC layout not including any active fins. A first portion of the empty region is filled with a first plurality of dummy fin cells, wherein each of the first plurality of dummy fin cells is based on a first standard dummy fin cell, and wherein the first standard dummy fin cell has a first gate width and comprises a first plurality of partitions. A second portion of the empty region is filled with a second plurality of dummy fin cells, wherein each of the second plurality of dummy fin cells is based on a second standard dummy fin cell, and wherein the second standard dummy fin cell has a second gate width and comprises a second plurality of partitions.

Claims21

Dependent claims

A method of forming an integrated circuit (IC) layout, comprising:

identifying, by a processor circuit, an empty region in the IC layout, wherein the empty region is a region of the IC layout not including any active fins;
filling a first portion of the empty region with a first plurality of dummy fin cells, wherein each of the first plurality of dummy fin cells is based on a first standard dummy fin cell, and wherein the first standard dummy fin cell has a first gate width and comprises a first plurality of partitions;
and
filling a second portion of the empty region with a second plurality of dummy fin cells, wherein each of the second plurality of dummy fin cells is based on a second standard dummy fin cell, and wherein the second standard dummy fin cell has a second gate width different from the first gate width and comprises a second plurality of partitions.

1 more element

A method of forming an integrated circuit (IC) layout, comprising:

filling a first portion of an empty region surrounding a device region of the IC layout with a first plurality of dummy fin cells, wherein the empty region is a region of the IC layout not including any active fins, and wherein each of the first plurality of dummy fin cells is based on a first standard dummy fin cell, and the first dummy fin cells comprise a first plurality of partitions;
and
filling a second portion of the empty region with a second plurality of dummy fin cells, wherein each of the second plurality of dummy fin cells is based on a second standard dummy fin cell, and the second dummy fin cells comprise a second plurality of partitions, wherein a quantity of the second plurality of partitions is greater than a quantity of the first plurality of partitions, and wherein at least one of the second plurality of dummy fin cells is larger than the second standard dummy fin cell along at least one dimension.

Dependencies are inferred from the claim text.

Dummy fin cell placement in an integrated circuit layout

Life of this patent

Dummy fin cell placement in an integrated circuit layout

Life of this patent

Abstract

Claims21