Integrated circuit design verification
AssigneeInternational Business Machines Corporation
InventorsAnand B. Arunagiri, Raj K. Gajavelly, Sujeet Kumar, Pradeep K. Nalla
Life of this patent
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Abstract
Disclosed aspects relate to verifying an integrated circuit design. A set of design constraints may be received with respect to a verification process for the integrated circuit design. Based on the set of design constraints, a constraint model may be constructed. A new global constraint may be determined using the constraint model. The new global constraint may be used to process the verification process for the integrated circuit design.
Claims20
A computer-implemented method for verifying an integrated circuit design, the method comprising:
- receiving, with respect to a verification process for the integrated circuit design, a set of design constraints;
- constructing, based on the set of design constraints, a constraint model;
- determining, using the constraint model, a new global constraint;
- and
- processing, using the new global constraint, the verification process for the integrated circuit design.
A system for verifying an integrated circuit design, the system comprising:
- a memory having a set of computer readable computer instructions, and
- a processor for executing the set of computer readable instructions, the set of computer readable instructions including:
- receiving, with respect to a verification process for the integrated circuit design, a set of design constraints;
- constructing, based on the set of design constraints, a constraint model;
- determining, using the constraint model, a new global constraint;
- and
- processing, using the new global constraint, the verification process for the integrated circuit design.
A computer program product for verifying an integrated circuit design, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a processor to cause the processor to perform a method comprising:
- receiving, with respect to a verification process for the integrated circuit design, a set of design constraints;
- constructing, based on the set of design constraints, a constraint model;
- determining, using the constraint model, a new global constraint;
- and
- processing, using the new global constraint, the verification process for the integrated circuit design.
Dependencies are inferred from the claim text.