Method and Apparatus for Collecting Signal Values in FPGA Based Emulation Machine
AssigneeSynopsys, Inc.
InventorMikhail Bershteyn
Life of this patent
Estimating the term…
Abstract
Systems and methods for collecting signal values in FPGA based emulation machine. A single LUT is used to observe three observable points within a VLSI. A 6-input LUT is used to implement scan cells. Each scan cell implements a 4:1 multiplexer using the 6-input LUT. Each scan cell also uses three registers. The first and second register are used to sample and hold signals from the first two of the three observable points associated with that scan cell. The third register is used to capture the output of the 4:1 multiplexer.
Claims6
A scan cell of a field programmable logic array (FPGA) based emulation machine, the scan cell comprising:
- a) four scan cell data inputs,
- b) a scan cell data output;
- c) two scan cell selection control inputs;
- d) a scan cell clock input;
- e) a first register having a register clock input coupled to the scan cell clock input, a D-input coupled to a first of the three scan cell data inputs and a Q-output;
- f) a second register having a register clock input coupled to the scan cell clock input, a D-input coupled to a second of the three scan cell data inputs and a Q-output;
- g) a multiplexer having 4 multiplexer data inputs, two multiplexer selection control inputs and a multiplexer data output:
- i. the first multiplexer data input coupled to the Q-output of the first register;
- ii. the second multiplexer data input coupled to the Q-output of the second register;
- iii. the third multiplexer input coupled to the third scan cell data input;
- and
- iv. the fourth multiplexer input coupled to the fourth scan cell data input;
- v. the first multiplexer selection control input coupled to a first of the two scan cell selection control inputs;
- vi. the second multiplexer selection control input coupled to the second scan cell selection control input;
- and
- h) third register having a register clock input coupled to the scan cell clock input, a D-input coupled to the multiplexer data output and a Q-output coupled to the scan cell data output.
A field programmable logic array (FPGA) based emulation machine comprising:
- a) one look up table (LUT) for each of N observable points in a user logic;
- and
- b) N registers, one of the N registers coupled to the output of the LUT.
A can cell of a field programmable logic array (FPGA) based emulation machine, the scan cell comprising:
- a) N scan cell data inputs,
- b) a scan cell data output;
- c) M scan cell selection control inputs, where M=Log2 (N);
- d) a scan cell clock input;
- e) a multiplexer having N multiplexer data inputs, M multiplexer selection control inputs and a multiplexer data output:
- N−1 registers, each having a register clock input coupled to the scan cell clock input, a D-input, the D-input of N−2 of the registers coupled to a corresponding one of N−2 of the scan cell data inputs in a one to one relationship, N−2 of the multiplexer data inputs are coupled to the Q-output of a corresponding one of the N−2 registers, in a one to one relationship, the Nth multiplexer input coupled to the Nth scan cell data input, each of the M multiplexer selection control inputs are coupled to a corresponding one of the M scan cell selection control inputs in a one to one relationship, the N−1st register having a D-input coupled to the multiplexer data output and a Q-output coupled to the scan cell data output.
Dependencies are inferred from the claim text.