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AssigneeSynopsys, Inc.
InventorsDeep Shah, Namit Gupta, Mohamed Shaker Sarwary
Estimating the term…
Information from a circuit design's unified power format (UPF) description is utilized to automate the management of reset domain crossings (RDCs). The UPF description is utilized to identify signals that generate both RDC and power domain crossings (PDCs), thereby allowing a circuit designer to efficiently utilize a common (shared) isolation circuit that functions to manage both the RDC (i.e., during reset functions) and the PDC (i.e., during power management functions). A modified UPF description is introduced that facilitates automated management of RDC issues by treating the reset domains as pseudo-power domains, and utilizing UPF analysis and verification tools to automatically generate both shared and non-shared resources for both RDC and PDC issues.
A method of efficiently addressing reset domain crossings (RDCs) and power domain crossings (PDCs) in an initial circuit design, said initial circuit design including a plurality of circuit structures and a plurality of signals passing between said plurality of circuit structures, said initial circuit design being defined by an initial Hardware Description Language (HDL) description in which each of said plurality of circuit structures is assigned to an associated reset domain of a plurality of reset domains such that one or more of said plurality of signals forms a corresponding said RDC between two reset domains of said plurality of reset domains, said initial circuit design being further defined by an initial Unified Power Format (UPF) description in which each of said plurality of circuit structures is further assigned to an associated power domain of a plurality of power domains such that one or more of said plurality of signals forms a corresponding said PDC between two power domains of said plurality of power domains, the method comprising:
A method for verifying a circuit design utilized to fabricate an integrated circuit (IC), the circuit design including a plurality of reset domains and power domains, the method comprising utilizing a UPF description of the circuit design to identify at least one signal that forms a reset domain crossing (RDC) by way of being transmitted between two reset domains of said plurality of reset domains, and also forms a power domain crossing (PDC) by way of being transmitted between two power domains of said plurality of power domains.
An EDA software tool comprising means for verifying a circuit design utilized to fabricate an integrated circuit (IC), the circuit design including a plurality of reset domains and power domains, said verifying means including means for analyzing a UPF description of the circuit design to identify at least one signal that forms a reset domain crossing (RDC) by way of being transmitted between two reset domains of said plurality of reset domains, and also forms a power domain crossing (PDC) by way of being transmitted between two power domains of said plurality of power domains.
Dependencies are inferred from the claim text.