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US 2018/0004791 A1Published application
Vertical transistor and method of forming the vertical transistor
AssigneeInternational Business Machines Corporation
InventorsFee Li LIE, Shogo MOCHIZUKI, JunIi WANG
Life of this patent
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Abstract
A method of forming a vertical transistor includes forming a fin structure on a substrate, forming a gate structure on the fin structure, and forming a bottom source/drain (S/D) region on the fin structure, such that an air gap is formed between the bottom S/D region and the gate structure.
Claims20
A method of forming a vertical transistor comprising:
- forming a fin structure on a substrate;
- forming a gate structure on the fin structure;
- and
- forming a bottom source/drain (S/D) region on the fin structure, such that an air gap is formed between the bottom S/D region and the gate structure.
1 more element
A method of forming a vertical transistor comprising:
- forming a cavity on a substrate;
- forming a fin structure over the cavity on the substrate;
- forming a gate structure over the cavity on the fin structure;
- and
- forming a bottom source/drain (S/D) region in the cavity on the fin structure.
2 more elements
A method of forming a vertical transistor comprising:
- forming an insulating layer on a substrate;
- forming a cavity in the insulating layer such that a surface of the substrate is exposed through the cavity;
- forming a fin structure over the cavity on the substrate;
- forming a gate structure over the cavity on the fin structure, the gate structure having a width which is less than a width of the cavity, and the gate structure comprising:
- end portions which contact a surface of the insulating layer on opposing sides of the cavity;
- and
- a central portion which is formed over the cavity;
- and
- forming a bottom source/drain (S/D) region in the cavity on the fin structure, such that an upper surface of the bottom S/D region is formed outside of the gate structure in a plan view.
6 more elements
Dependencies are inferred from the claim text.