System and method for gpu maximum register count optimization applied to general matrix-matrix multiplication
AssigneePalo Alto Research Center Incorporated
InventorRong Zhou
Life of this patent
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AssigneePalo Alto Research Center Incorporated
InventorRong Zhou
Estimating the term…
A method and system performing a general matrix-matrix multiplication (GEMM) operation using a kernel compiled with optimal maximum register count (MRC). During operation, the system may generate the kernel compiled with optimal MRC. This may involve determining a fastest compiled kernel among a set of compiled kernels by comparing the speeds of the compiled kernels. Each kernel may be compiled with a different MRC value between zero and a predetermined maximum number of registers per thread. The fastest compiled kernel is determined to be the kernel with optimal MRC. The system may receive data representing at least two matrices. The system may select the kernel compiled with optimal MRC, and perform the GEMM operation on the two matrices using the selected kernel. Some embodiments may also perform general matrix-vector multiplication (GEMV), sparse matrix-vector multiplication (SpMV), or k-means clustering operations using kernels compiled with optimal MRC.
A computer-executable method for performing a general matrix-matrix multiplication (GEMM) operation using a kernel compiled with optimal maximum register count (MRC), comprising:
A non-transitory computer-readable storage medium storing instructions which when executed by a computer cause the computer to perform a method for general matrix-matrix multiplication (GEMM) using a kernel compiled with optimal maximum register count (MRC), the method comprising:
A computing system comprising:
Dependencies are inferred from the claim text.