Graphics processing unit (gpu) as a programmable packet transfer mechanism
AssigneeIntel Corporation
InventorsChris MacNamara, Tomasz Kantecki, John J. Browne
Life of this patent
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Abstract
Discloses is an apparatus including a network interface controller (NIC), memory, and an accelerator. The accelerator can include a direct memory access (DMA) controller configured to receive data packets from the NIC and to provide the data packets to the memory. The accelerator can also include processing circuitry to generate processed data packets by implementing packet processing functions on the data packets received from the NIC, and to provide the processed data packets to at least one processing core. Other methods, apparatuses, articles and systems are also described
Claims24
An apparatus comprising:
- a network interface controller (NIC);
- memory;
- and
- an accelerator comprising:
- a direct memory access (DMA) controller configured to receive data packets from the NIC and to move the data packets to the memory;
- and
- processing circuitry configured to
- generate processed data packets by implementing packet processing functions on the data packets received from the NIC, and
- provide the processed data packets to at least one processing core of a central processing unit (CPU).
A system comprising:
- a network interface controller (NIC) configured to transmit and receive data from a network;
- a central processing unit (CPU) including a first core and a second core;
- an accelerator in electrical communication with the CPU and the NIC, the accelerator including a direct memory access (DMA) controller, processing circuitry and a memory, the accelerator to perform operations comprising:
- generating processed data packets by implementing packet processing functions on the data packets received from the NIC, and
- providing the processed data packets to at least one of the first core or the second core.
A machine-readable medium storing instruction that, when executed by a graphics processing unit (GPU), cause the GPU to perform operations comprising:
- providing data packets from a network interface controller (NIC) at a direct memory access (DMA) controller of the GPU;
- processing the data packets using packet processing functions, the packet processing functions including at least one of a decryption function and a packet classifier function, to generate processed data packets;
- and
- providing the processed data packets to at least one processing core of a central processing unit (CPU).
A graphics processing unit (GPU) comprising:
- means for transmitting and receiving data packets to and from a network;
- means for transmitting processed data packets to a plurality of cores of a central processing unit (CPU);
- and
- means for generating the processed data packets for transmission to the plurality of cores.
Dependencies are inferred from the claim text.