Load reduced nonvolatile memory interface
AssigneeIntel Corporation
InventorsEmily CHUNG, Frank T. HADY, George VERGIS
Life of this patent
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Abstract
A storage circuit includes a buffer coupled between the storage controller and the nonvolatile memory devices. The circuit includes one or more groups of nonvolatile memory (NVM) devices, a storage controller to control access to the NVM device, and the buffer. The buffer is coupled between the storage controller and the NVM devices. The buffer is to re-drive signals on a bus between the NVM devices and the storage controller, including synchronizing the signals to a clock signal for the signals. The circuit can include a data buffer, a command buffer, or both.
Claims22
A system, comprising:
- a group of nonvolatile memory (NVM) devices;
- a storage controller coupled to the group of NVM devices, the storage controller to manage reading and writing to the NVM devices;
- and
- a data buffer coupled between the group of NVM devices and the storage controller on a data bus, the data buffer to re-drive data signals on the data bus, and synchronize data signals to a clock signal.
A solid state drive (SSD), comprising:
- a storage controller including an interface to couple to a host processor, the storage controller to manage read and write requests from the host processor;
- and
- multiple storage circuits coupled to the storage controller, including
- a plurality of nonvolatile memory (NVM) devices;
- and
- a data buffer coupled between the plurality of NVM devices and the storage controller on a data bus, the data buffer to re-drive data signals on the data bus, and synchronize data signals to a clock signal.
A method for data access, comprising:
- receiving a buffer command at a buffer coupled between a group of nonvolatile memory (NVM) devices and a storage controller, the buffer command to be issued after a data access command issued to the group of NVM devices;
- and
- responsive to receiving the buffer command, re-driving data signals on a data bus between the NVM devices and the storage controller, including synchronizing the data signals to a clock signal.
Dependencies are inferred from the claim text.