Method and apparatus of real-time retimer delay measurement

A retimer component comprising:

• an elastic buffer circuitry comprising a write-clock input coupled to a recovered-clock path, a write-data input coupled to a recovered-clock data path, a read-clock input coupled to a local-clock path, and a read-data output coupled to a local-clock data path;
• a first flag circuitry to assert a recovered-clock flag signal when a set of one or more values on the recovered-clock data path matches part of a set of skip-ordered-set values over a corresponding set of cycles of a recovered-clock signal on the recovered-clock path;
• a second flag circuitry to assert a local-clock flag signal when a set of one or more values on the local-clock data path matches part of the set of skip-ordered-set values over a corresponding set of cycles of a local-clock signal on the local-clock path;
• and
• a counter circuitry to increment a count value with cycles of a local-clock signal on the local-clock path,
• wherein the counter circuitry is to reset the count value and start incrementing upon assertion of the recovered-clock flag signal;
• and
• wherein the counter circuitry is to stop incrementing upon assertion of the local-clock flag signal.

A system comprising a memory, a processor coupled to the memory, and a wireless interface for allowing the processor to communicate with another device, the processor including:

• a first circuitry comprising a data input coupled to a first data path, a data output coupled to a second data path, a write-clock input coupled to a first clock path, and a read-clock input coupled to a second clock path;
• a second circuitry to assert a first flag when a set of one or more values on the first data path matches a portion of a set of one or more predetermined values over a corresponding set of one or more cycles of a clock on the first clock path;
• a third circuitry to assert a second flag when a set of one or more values on the second data path matches a portion of the set of one or more predetermined values over a corresponding set of one or more cycles of a clock on the second clock path;
• and
• a fourth circuitry to begin incrementing a count value upon assertion of a first flag input coupled to the first flag and to stop incrementing the count value upon assertion of a second flag input coupled to the second flag.