Efficient low cost on-die configurable bridge controller

An apparatus comprising:

• a host controller;
• a device controller;
• and
• a bridge controller coupled to the host controller by a first interface and coupled to the device controller by a second interface, the bridge controller comprising:
• a downstream translation circuitry to process a transaction received on the first interface and to generate a transaction for the second interface;
• an upstream translation circuitry to process a transaction received on the second interface and to generate a transaction for the first interface;
• and
• a state machine incorporating sequential logic to set a line-state output of the first interface to a value that is one of:
• a single-ended-zero-state (SE0-state) value, a J-state value, or a K-state value,
• wherein the state machine is to have a line-state state that is any of:
• a reset state, a full-speed-detect state, a low-speed-detect state, a host-drive-SE0 state, a device-response-K state, a device-response-SQ state, a host-response-JK state, an idle-done state, or a full-speed-low-speed-reset state;
• and
• wherein the host controller is to generate a transaction for the first interface based at least in part upon the state of the line-state output;
• and
• wherein the device controller is to generate a transaction for the second interface based at least in part upon the state of the line-state output.

A system comprising a memory, a processor coupled to the memory, a wireless interface for allowing the processor to communicate with another device, and a computing device comprising:

• an interface comprising a line-state output;
• and
• a state machine to set the line-state output to a value that is one of:
• a single-ended-zero-state (SE0-state) value, a J-state value, or a K-state value,
• wherein the state machine is to have a line-state state that is one of:
• a reset state, a full-speed-detect state, a low-speed-detect state, a host-drive-SE0 state, a device-response-K state, a device-response-SQ state, a host-response-JK state, an idle-done state, or a full-speed-low-speed-reset state;
• and
• wherein the value of the line-state output is based at least in part upon the line-state state.