Processors, methods, systems, and instructions to support live migration of protected containers

A method of performing from one to three machine instructions in a processor to perform operations comprising:

• write protecting a page of a protected container memory;
• ensuring that no writable permissions for the page of the protected container memory are cached in the processor;
• encrypting a copy of the page of the protected container memory;
• storing the encrypted copy of the page of the protected container memory to a storage location that is outside of the protected container memory, after said ensuring that there are no writable references to the write protected page of the protected container memory;
• and
• leaving the write protected page of the protected container memory in a valid and readable state after said storing the encrypted copy of the page of the protected container memory to the storage location that is outside of the protected container memory.

A system to process instructions comprising:

• an interconnect;
• a processor coupled with the interconnect, the processor to receive an instruction, the instruction to indicate a page of a protected container memory, and to indicate a storage location outside of the protected container memory, the processor, in response to the instruction, to:
• ensure that there are no writable references to the page of the protected container memory, while the page of the protected container memory has a write protected state;
• encrypt a copy of the page of the protected container memory;
• store the encrypted copy of the page to the indicated storage location outside of the protected container memory, after it has been ensured that there are no writable references to the page of the protected container memory;
• and
• leave the page of the protected container memory in the write protected state, which is also to be valid and readable, after the encrypted copy of the page has been stored to the indicated storage location outside of the protected container memory;
• and
• a dynamic random access memory (DRAM) coupled with the interconnect.