Cache unit and processor

A processor comprising:

• a cache unit;
• and
• a CPU configured to perform operation of data acquired from the cache unit, wherein
• the cache unit comprises:
• a first memory configured to temporarily hold the data and an address of the data;
• a second memory configured to temporarily hold an address of a particular data set in advance, the particular data being not held by the first memory;
• and
• a controller configured to, when a first address is specified by the CPU and an instruction to load data is made, search for a storage destination of the first specified address, output the data of the first specified address if the storage destination is the first memory, and output the particular data to the CPU if the storage destination is the second memory, and configured to, when an instruction to store specified data at a second specified address is made by the CPU, judge whether the specified data is the particular data or not, store the second specified address and the specified data into the first memory if the specified data is not the particular data, and store the second specified address into the second memory if the specified data is the particular data.

A cache unit comprising:

• a first memory configured to temporarily hold first data and an address of the first data;
• a second memory configured to temporarily hold an address of a particular data set in advance, the particular data being not held by the first memory;
• a buffer configured to hold second data and an address of the second data to be provided to the first memory and the second memory;
• and
• a controller configured to, when an instruction to store specified data at a second specified address is made, judge whether the specified data is the particular data or not, store the second specified address and the specified data into the first memory if the specified data is not the particular data, and store the second specified address into the second memory if the specified data is the particular data.

A cache unit comprising:

• a first memory configured to hold data and an address of the data;
• a second memory configured to hold an address of a particular data;
• a controller configured to, when an instruction to load data is made for a first address, search for a storage destination of the first address, output the data of the first address if the storage destination is the first memory, and output the particular data if the storage destination is the second memory, wherein
• when an instruction to store data at a second address is made, the controller stores the second address into the second memory if the data to be stored is the particular data.