Prefetch bandwidth throttling by dynamically adjusting miss buffer prefetch-dropping thresholds

A processor with a mechanism that controls prefetching to prevent over-saturation of interfaces in a memory hierarchy of the processor, comprising:

• a processor core;
• a single or multilevel cache that is part of the memory hierarchy;
• bandwidth-determination logic that determines a bandwidth utilization of an interface from the cache to a lower level of the memory hierarchy;
• and
• a miss buffer associated with the cache that stores entries for outstanding demand requests and prefetches that missed in the cache and are waiting for corresponding data to be returned from the lower level of the memory hierarchy;
• wherein the miss buffer selectively adjusts a prefetch-dropping high-water mark for occupancy of the miss buffer based on the determined bandwidth utilization;
• and
• wherein when an occupancy of the miss buffer exceeds the prefetch-dropping high-water mark, subsequent prefetches that cause a cache miss are dropped.

A computer system, comprising:

• a processor;
• and
• a memory hierarchy, which includes a cache hierarchy and a memory;
• wherein the processor comprises,
• a processor core,
• the cache hierarchy that includes one or more caches;
• bandwidth-determination logic that determines a bandwidth utilization of an interface from the cache to a lower level of the memory hierarchy, and
• a miss buffer associated with the cache that stores entries for outstanding demand requests and prefetches that missed in the cache and are waiting for corresponding data to be returned from the lower level of the memory hierarchy,
• wherein the miss buffer selectively adjusts a prefetch-dropping high-water mark for occupancy of the miss buffer based on the determined bandwidth utilization, and
• wherein when an occupancy of the miss buffer exceeds the prefetch-dropping high-water mark, subsequent prefetches that cause a cache miss are dropped.