Direct store to coherence point
AssigneeMicrosoft Technology Licensing, LLC
InventorsPatrick P. Lai, Robert Allen Shearer
Life of this patent
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Abstract
A system that uses a write-invalidate protocol has at least two types of stores. A first type of store operation uses a write-back policy resulting in snoops for copies of the cache line at lower cache levels. A second type of store operation writes, using a coherent write-through policy, directly to the last-level cache without snooping the lower cache levels. By storing directly to the coherence point, where cache coherence is enforced, for the coherent write-through operations, snoop transactions and responses are not exchanged with the other caches. A memory order buffer at the last-level cache ensures proper ordering of stores/loads sent directly to the last-level cache.
Claims20
An integrated circuit, comprising:
- a plurality of processor cores that share a common last-level cache, the plurality of processor cores including at least a first processor core;
- and,
- a memory order buffer to receive store transactions sent to the last-level cache, the store transactions to include first transactions that are indicated by the first processor core to be written directly to the common last-level cache, the store transactions to include second transactions that are indicated by the first processor core to be processed by a lower-level cache before being sent to the last-level cache.
A method of operating a processing system, comprising:
- receiving, from a plurality of processor cores, a plurality of store transactions at a common last-level cache, the plurality of processor cores including a first processor core;
- issuing, by the first processor core and to the common-last level cache, at least a first store transaction and a second store transaction, the first store transaction to be indicated to be written directly to the common last-level cache, the second store transaction to be indicated to be processed by a lower-level cache before being sent to the last-level cache;
- and,
- receiving, at a memory order buffer, the first store transaction and data stored by the second store transaction.
A processing system, comprising:
- a plurality of processing cores each coupled to at least a first level cache;
- a last-level cache, separate from the first level cache, to receive store data from the first level cache and the plurality of processing cores;
- and,
- a memory order buffer, coupled to the last-level cache, to receive a first line of store data from the first level cache and to receive a second line of store data from a first processing core of the plurality of processing cores without the second line of store data being processed by the first level cache.
Dependencies are inferred from the claim text.