Bit check processors, methods, systems, and instructions to check a bit with an indicated check bit value
AssigneeIntel Corporation
InventorsHugh Wilkinson, William R. Wheeler, Debra Bernstein
Life of this patent
Estimating the term…
Abstract
A processor of an aspect includes a register to store a condition code bit, and a decode unit to decode a bit check instruction. The bit check instruction is to indicate a first source operand that is to include a first bit, and is to indicate a check bit value for the first bit. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the bit check instruction, is to compare the first bit with the check bit value, and update a condition code bit to indicate whether the first bit equals or does not equal the check bit value. Other processors, methods, systems, and instructions are disclosed.
Claims25
A processor comprising:
- a register to store a condition code bit;
- a decode unit to decode a bit check instruction, the bit check instruction to indicate a first source operand that is to include a first bit, and to indicate a check bit value for the first bit;
- and
- an execution unit coupled with the decode unit, the execution unit, in response to the bit check instruction, to:
- compare the first bit with the check bit value;
- and
- update the condition code bit to indicate whether the first bit equals or does not equal the check bit value.
A method performed by a processor comprising:
- receiving a bit check instruction at the processor, the bit check instruction indicating a first source operand that includes a first bit, and indicating a check bit value for the first bit;
- comparing the first bit with the check bit value in response to the bit check instruction;
- and
- updating a condition code bit to indicate whether the first bit equals or does not equal the check bit value in response to the bit check instruction.
A system to process instructions comprising:
- an interconnect;
- a processor coupled with the interconnect, the processor to receive a bit check instruction that is to indicate a first source operand that is to include a first bit, and is to indicate a check bit value for the first bit, the processor, in response to the bit check instruction, to compare the first bit with the check bit value, and update a condition code bit to indicate whether the first bit equals or does not equal the check bit value;
- and
- a dynamic random access memory (DRAM) coupled with the interconnect.
An article of manufacture comprising a non-transitory machine-readable storage medium, the non-transitory machine-readable storage medium storing a plurality of instructions including a bit check instruction, the bit check instruction, if executed by a machine, is to cause the machine to perform operations comprising:
- access a first source operand, which is to be indicated by the bit check instruction, the first source operand to include a first bit;
- access a check bit value for the first bit, which is to be indicated by the bit check instruction;
- compare the first bit with the check bit value in response to the bit check instruction;
- and
- update a condition code bit to indicate whether the first bit equals or does not equal the check bit value in response to the bit check instruction.
Dependencies are inferred from the claim text.