Memory controller and memory system including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsMOOSUNG KIM, DAWOON JUNG
Life of this patent
Estimating the term…
Abstract
An operating method is for a memory device which controls a nonvolatile memory. The operating method includes managing a program depth bit map indicating an upper page program state of each of a plurality of word lines of the nonvolatile memory in response to an external write request, and outputting one of a plurality of different read commands to the nonvolatile memory based on information of the program depth bit map corresponding to a word line to be accessed in response to an external read request.
Claims12
A read method of a nonvolatile memory device, comprising:
- determining whether an input read command is a read command for a word line having an upper page program state;
- when the input read command is determined not to be a read command for a word line having an upper page program state, performing a first lower page read operation on the word line;
- when the input read command is determined to be a read command for a word line having an upper page program state, determining whether a page address input together with the input read command is a lower page address;
- when the page address input together with the input read command is determined to be the lower page address, performing a second lower page read operation on the word line;
- and
- when the page address input together with the input read command is determined not to be the lower page address, performing an upper page read operation on the word line.
The read method of claim 23, wherein the nonvolatile memory device includes a flag cell for storing a program state of the word line, and wherein the flag cell is not accessed in response to the input read command.
A nonvolatile memory device, comprising:
- a memory cell array including memory cells arranged in rows and columns;
- a read/write circuit configured to read data from the memory cell array and to store data at the memory cell array;
- and
- control logic configured to control the read/write circuit in response to a read command provided from an external device,
- wherein the control logic determines whether the read command is a first read command directing a read operation on a word line having a lower page program state or a second read command directing a read operation on a word line having an upper page program state;
- and
- wherein when the read command is determined to be the second read command, the control logic controls the read/write circuit to read a lower page or an upper page of a word line based on a page address input with the second read command.
Dependencies are inferred from the claim text.