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US 2018/0004628 A1Published application
Cooperative triggering
AssigneeIntel Corporation
InventorsBeeman C. Strong, Matthew C. Merten, Lee W. Baugh
Life of this patent
Estimating the term…
Abstract
There is disclosed in an example a processor, having: a front end including circuitry to decode instructions from an instruction stream; a data cache unit including circuitry to cache data for the processor; and a core triggering block (CTB) to provide integration between two or more different debug capabilities.
Claims26
A processor, comprising:
- a front end including circuitry to decode instructions from an instruction stream;
- a data cache unit including circuitry to cache data for the processor;
- a core triggering block (CTB) to provide integration between two or more different debug capabilities.
A method of providing visibility features for a processor, comprising:
- communicatively coupling to a front end having instruction decode circuitry;
- communicatively coupling to a data cache having circuitry to cache data for the processor;
- and
- integrating two or more different debug capabilities of the processor within a core triggering block (CTB).
1 more element
A core triggering block (CTB), comprising:
- circuitry to communicatively couple to a front end having instruction decode circuitry;
- communicatively couple to a data cache having circuitry to cache data for the processor;
- and
- circuitry to integrate two or more different debug capabilities of a microprocessor.
1 more element
Dependencies are inferred from the claim text.