System, method, and computer program for protecting data in persistent memory
AssigneeLenovo Enterprise Solutions (Singapore) Pte. Ltd.
InventorsMakoto Ono, Sumeet Kochar, Nagananda Chumbalkar
Life of this patent
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Abstract
According to one embodiment, a computer program embodied on a tangible computer readable medium includes computer code for identifying a first write to a first persistent memory on a first channel and a second write to a second persistent memory on a second channel, computer code for performing a third write to a third persistent memory on a third channel, where the third write includes parity data associated with the first write and the second write, computer code for identifying a failure of the second persistent memory, and computer code for generating recovery data for the second persistent memory, using the first channel, the third channel, and the parity data.
Claims20
A computer program embodied on a tangible computer readable medium, comprising:
- computer code for identifying a first write to a first persistent memory on a first channel and a second write to a second persistent memory on a second channel;
- computer code for performing a third write to a third persistent memory on a third channel, where the third write includes parity data associated with the first write and the second write;
- computer code for identifying a failure of the second persistent memory;
- and
- computer code for generating recovery data for the second persistent memory, using the first channel, the third channel, and the parity data.
A method, comprising:
- identifying a first write to a first persistent memory on a first channel and a second write to a second persistent memory on a second channel;
- performing a third write to a third persistent memory on a third channel, where the third write includes parity data associated with the first write and the second write;
- identifying a failure of the second persistent memory;
- and
- generating recovery data for the second persistent memory, using the first channel, the third channel, and the parity data.
A system, comprising:
- a processor and logic integrated with and/or executable by the processor, the logic being configured to:
- identify a first write of first data to a first persistent memory on a first channel and a second write of second data to a second persistent memory on a second channel;
- generate a parity block by performing an XOR operation on the first data and the second data;
- perform a third write of the parity block to a third persistent memory on a third channel;
- identify a failure of the second persistent memory;
- and
- recreate the second data, using the first data, the parity block, and the XOR operation.
Dependencies are inferred from the claim text.