US 2018/0004602 A1Published application

Method of correcting errors in a memory array and a system for implementing the same

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsYu-Der CHIH, Chia-Fu LEE, Chien-Yin LIU, Yi-Chun SHIH, Kuan-Chun CHEN, Hsueh-Chih YANG, Shih-Lien Linus LU

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Abstract

A method of correcting errors in a memory array. The method includes configuring a first memory array with a first error correction code (ECC) to provide error correction of data stored in the first memory array, configuring a second memory array with a second ECC to provide error correction of the data stored in the first memory array, performing a reflow process on the first and second memory array, and correcting data stored in the first memory array based on at least the first ECC or the second ECC. The first memory array includes a first set of memory cells arranged in rows and columns. The second memory array includes a second set of memory cells arranged in rows and columns.

Claims20

Dependent claims

A method of correcting errors in a memory array, the method comprising:

configuring a first memory array with a first error correction code (ECC) to provide error correction of data stored in the first memory array, the first memory array including a first set of memory cells arranged in rows and columns, a row of memory cells in the first set of memory cells includes a first set of memory words, each word of the first set of memory words includes a first set of bits;
configuring a second memory array with a second ECC to provide error correction of the data stored in the first memory array, the second memory array including a second set of memory cells arranged in rows and columns, a row of memory cells in the second set of memory cells includes a second set of memory words, each word of the second set of memory words includes a second set of bits;
performing a reflow process on the first memory array and the second memory array;
and
correcting data stored in the first memory array based on at least the first ECC or the second ECC.

2 more elements

A method of correcting errors in a memory array, the method comprising:

configuring a first memory array with a first error correction code (ECC) to provide error correction of data stored in the first memory array, the first memory array including a first set of memory cells arranged in rows and columns, a row of memory cells in the first set of memory cells includes a first set of memory words, each word of the first set of memory words includes a first set of bits;
configuring a first portion of a second memory array with a first parity check configured to provide error detection of the data stored in the rows of the first memory array, the first portion of the second memory array including a second set of memory cells storing a first set of data;
configuring a second portion of the second memory array with a second parity check configured to provide error detection of the data stored in the columns of the first memory array, the second portion of the second memory array including a third set of memory cells storing a second set of data;
configuring the second portion of the second memory array with a second ECC to provide error correction of the second set of data stored in the second portion of the second memory array;
performing a reflow process on the first memory array and the second memory array;
correcting at least a portion of the data stored in the first memory array based on at least the first ECC or the first parity check and the second parity check;
and
correcting the second set of data stored in the second portion of the second memory array based on the second ECC.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/634,876Filed 27 Jun 2017
Priority: 30 Jun 2016
Published: 4 Jan 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

G06F 11/1076
Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's: parity data used in redundant arrays of…
G06F 11/1012
In individual solid state devices: using codes or arrangements adapted for a specific type of error
G06F 11/1048
In individual solid state devices: using arrangements adapted for a specific error detection or correction feature
H03M 13/2906
Combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes: using…