US 2018/0004599 A1Published application

Methods for Error Correction with Resistive Change Element Arrays

AssigneeNantero, Inc.

InventorSheyang NING

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Abstract

Error correction methods for arrays of resistive change elements are disclosed. An array of resistive change elements is organized into a plurality of subsections. Each subsection includes at least one flag bit and a plurality of data bits. At the start of a write operation, all bits in a subsection are initialized. If any data bits fail to initialize, the pattern of errors is compared to the input data pattern. The flag cells are then activated to indicate the appropriate encoding pattern to apply to the input data to match the errors. The input data is then encoded according to this encoding pattern before being written to the array. A second error correction algorithm can be used to correct remaining errors. During a read operation, the encoding pattern indicated by the flag bits is used to decode the read data and retrieve the original input data.

Claims34

Dependent claims

A method of error correction for a resistive change element array comprising:

providing a resistive change element array, said resistive change element array comprising:
a plurality of resistive change elements, each of said plurality of resistive change elements capable of adjusting between at least two non-volatile resistive states responsive to applied electrical stimuli, wherein one of said non-volatile resistive states is an initialized state;
wherein said plurality of resistive change elements within said array are organized into a plurality of subsections, each of said subsections including a plurality of resistive change elements assigned as data cells and at least one resistive change element assigned as a flag cell, said data cells further organized into a plurality of data subsets, each of said data subsets having at least two data cells;
receiving input data to be programmed into at least one of said subsections;
initializing all of said data cells and said flag cells within at least one of said subsections into said initialized state;
reading said data cells within said at least one subsection to identify any data subsets with initialization errors;
comparing said identified data subsets within said at least one subsection with initialization errors to said input data to select an encoding pattern capable of correcting at least one of said initialization errors, said encoding pattern having a pattern reference code;
encoding said input data with said selected encoding pattern to obtain encoded input data;
programming said encoded input data into said data cells and said pattern reference code into said flag cells within said at least one subsection;
accessing at least one of said programmed subsections during a read operation to obtain encoded read data;
and
decoding said encoded read data according to an encoding pattern indicated by said flag cells within said at least one programmed subsection to generate output data;
wherein said encoding step provides a first error correction operation.

10 more elements

A method of encoding data for error correction, comprising:

providing a first set of data and a second set of data of equal length;
organizing said first set of data into a first plurality of subsets and said second set of data into a corresponding plurality of subsets, each of said subsets comprising an equal number of data bits, wherein the logical values of said data bits within each of said subsets forms a logical pattern;
comparing each bit within said first plurality of subsets which has a preselected logical value to its corresponding bit, wherein each of said bits which has a difference in logical value with its corresponding bit is an error bit and each subset within said first plurality of subsets containing at least one error bit is an error subset, the logical pattern of bits in said error subset being an error pattern;
matching said error subsets and said corresponding subsets to select an encoding pattern, said matching step comprising:
sorting each of said error subsets according to the logical pattern of its corresponding subset;
selecting a first logical pattern within said corresponding subsets which has the largest number of error subsets containing different error patterns to translate to a second logical pattern, and selecting a primary set of encoding patterns capable of said translation of said first logical pattern to said second logical pattern;
determining the logical pattern within said corresponding subsets which has the largest number of a single error pattern to translate to a logical pattern capable of correcting said single error pattern, and selecting a second set of encoding patterns from said primary set of encoding patterns capable of said translation;
repeating said determining step for each of said logical patterns within said corresponding subsets which has an associated error subset until a single encoding pattern is selected from said primary set of encoding patterns;
translating each of said subsets within said corresponding plurality of subsets into an encoded subset according to said selected encoding pattern to obtain an encoded set of data;
wherein said encoding pattern is selected from the set of all possible reversible translation patterns for the possible logical combinations of bits in a subset containing said number of data bits;
wherein said correction of said error bits comprises translating its corresponding bit to have a logical value equal that of said error bit according to said selected encoding pattern;
and
wherein said encoding pattern is selected to maximize the number of error bits corrected.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/621,757Filed 13 Jun 2017
Priority: 1 Jul 2016
Published: 4 Jan 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

G06F 11/1068
In individual solid state devices: in sector programmable memories, e.g. flash disk
G06F 11/1048
In individual solid state devices: using arrangements adapted for a specific error detection or correction feature
G11C 13/0069
Auxiliary circuits: writing or programming circuits or methods
G11C 29/44
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: indication or identification of errors, e.g. for…