Low-Overhead Mechanism to Detect Address Faults in ECC-Protected Memories
AssigneeIntel Corporation
InventorsKon-Woo KWON, Vivek KOZHIKKOTTU, Dinesh SOMASEKHAR
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Abstract
Embodiments are generally directed to a low-overhead mechanism to detect address faults in ECC-protected memories. An embodiment of an apparatus includes a memory array; an error correction code (ECC) encoder for the memory array to encode ECC values based on a data value and a respective address value for the data value; and an ECC decoder for the memory array to decode ECC values that are based on data values and respective addresses for the data values; wherein the apparatus is to detect and correct an error in an address value based on an ECC value, address value, and data value stored in the memory.
Claims23
An apparatus comprising:
- a memory array;
- an error correction code (ECC) encoder for the memory array to encode ECC values based on a data value and a respective address value for the data value;
- and
- an ECC decoder for the memory array to decode ECC values that are based on data values and respective addresses for the data values;
- wherein the apparatus is to detect and correct an error in an address value based on an ECC value, address value, and data value stored in the memory array.
The apparatus of claim 4, wherein the apparatus is to generate an address fault signal based on a value of the error location vector.
A method comprising:
- receiving a command to read a data value at an address value of a memory array;
- reading a data value and an error correction code (ECC) value based on the address, wherein the ECC value is generated based on the data value and the address value;
- performing a decoding operation using the requested address value and the data value and ECC value read from the memory array;
- and
- identifying one or more errors in the address value based on the decoding operation.
A computing system comprising:
- one or more processors for processing of data;
- a memory apparatus for the storage of data, the memory apparatus including a memory array;
- and
- a wireless transmitter or receiver and one or more antennae for the transmission or reception of data;
- the system further comprising error correction code (ECC) logic, including:
- an ECC encoder to encode ECC values based on a data value and a respective address value for the data value, and
- an ECC decoder to decode ECC values that are based on data values and respective addresses for the data values;
- wherein the ECC logic is to detect and correct an error in an address value based on an ECC value, address value, and data value stored in the memory array.
One or more non-transitory computer-readable storage mediums having stored thereon data representing sequences of instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
- receiving a command to read a data value at an address value of a memory array;
- reading a data value and an error correction code (ECC) value based on the address value, wherein the ECC value is generated based on the data value and the address value;
- performing a decoding operation using the requested address value and the data value and ECC value read from the memory array;
- and
- identifying one or more errors in the address value based on the decoding operation.
Dependencies are inferred from the claim text.