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US 2018/0004592 A1Published application
Delay-compensated error indication signal
AssigneeIntel Corporation
InventorsKuljit S. BAINS, George VERGIS
Life of this patent
Estimating the term…
Abstract
A memory subsystem has multiple memory devices coupled to a command/address line and an error alert line, the error alert line delay-compensated to provide deterministic alert signal timing. The command/address line and the error alert line are connected between the memory devices and a memory controller that manages the memory devices. The command/address line is driven by the memory controller, and the error alert line is driven by the memory devices.
Claims19
A memory module comprising:
- multiple memory devices to store data;
- a command/address transmission line coupled between each of the memory devices and a memory controller, wherein the command/address transmission line is driven by the memory controller;
- and
- an error alert transmission line coupled to each of the memory devices, wherein the error alert signal is driven by the memory devices, wherein the error alert transmission line is delay-compensated to provide a deterministic alert signal timing on the error alert transmission line.
1 more element
A memory subsystem comprising:
- a memory controller coupled to a command/address line and an error alert line;
- multiple memory devices that share the command/address line and the error alert line, the command/address line driven by the memory controller to the memory devices, and the error alert line driven by the memory devices to the memory controller;
- wherein the error alert line is delay-compensated to provide a deterministic alert signal timing on the error alert line.
An electronic device comprising:
- a memory subsystem having a memory controller coupled to a command/address line and an error alert line, and a memory module with multiple memory devices that share the command/address line and the error alert line, the command/address line driven by the memory controller to the memory devices, and the error alert line driven by the memory devices to the memory controller, wherein the error alert line is delay-compensated to provide a deterministic alert signal timing on the error alert line;
- and
- a multicore processor coupled to the memory subsystem to access the memory subsystem during execution of the processor.
Dependencies are inferred from the claim text.