Advanced processor architecture
AssigneeHyperion Core, Inc.
InventorMartin VORBACH
Life of this patent
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Abstract
The invention relates to a method for processing instructions out-of-order on a processor comprising an arrangement of execution units. The inventive method comprises: 1) looking up operand sources in a Register Positioning Table and setting operand input references of the instruction to be issued accordingly; 2) checking for an Execution Unit (EXU) available for receiving a new instruction; and 3) issuing the instruction to the available Execution Unit and enter a reference of the result register addressed by the instruction to be issued to the Execution Unit into the Register Positioning Table (RPT).
Claims4
A method for processing instructions out-of-order on a processor comprising an arrangement of execution units, the method comprising:
- looking up operand sources in a Register Positioning Table and setting operand input references of an instruction to be issued accordingly;
- checking for an Execution Unit (EXU) available for receiving a new instruction;
- and
- issuing the instruction to the available Execution Unit and entering a reference of a result register addressed by the instruction to be issued to the Execution Unit into the Register Positioning Table (RPT).
A processor core having an execution unit comprising an arrangement of Arithmetic-Logic-Units, wherein
- the operation mode of the execution unit is switchable between
- a) an asynchronous operation of the Arithmetic-Logic-Units and interconnection between the Arithmetic-Logic-Units
- such that a signal from the register file crosses the execution unit and is receipt by the register file in one clock cycle;
- and
- b) a pipelined operation mode of at least one of the Arithmetic-Logic-Units and the interconnection between the Arithmetic-Logic-Units
- such that a signal requires from the register file through the execution unit back to the register file more than one clock cycles.
Dependencies are inferred from the claim text.