Arithmetic processing device and control method of arithmetic processing device

A method for controlling an arithmetic processing device, the method comprising:

• generating an address for fetching an instruction by an address generation unit included in the arithmetic processing device;
• predicting a branch destination address of a branch instruction based on the address generated by the address generation unit, outputting the predicted branch destination address to the address generation unit, and predicting loop processing based on the address generated by the address generation unit by a branch prediction unit included in the arithmetic processing device;
• storing an instruction corresponding to the address generated by the address generation unit by an instruction buffer unit included in the arithmetic processing device;
• decoding the instruction stored in the instruction buffer unit by a first instruction decoding unit included in the arithmetic processing device;
• storing decoding results or decoding intermediate results of instructions of the predicted loop processing that are decoded by the first instruction decoding unit and outputting the stored decoding results or decoding intermediate results a predetermined number of times in response to the loop processing by a loop buffer unit included in the arithmetic processing device;
• and
• selecting either output of the loop buffer unit or output of the first instruction decoding unit by a selection unit included in the arithmetic processing device, wherein
• during a period when the selection unit selects the output of the loop buffer unit, the loop buffer unit stops operations of the address generation unit, the branch prediction unit, the instruction buffer unit, and the first instruction decoding unit.