Operation of a multi-slice processor implementing prioritized dependency chain resolution

A computer processor configured to carry out:

• receiving, from an instruction fetch unit of the computer processor, a first instruction and a branch instruction;
• responsive to determining that the branch instruction is dependent upon a result of the first instruction, updating a priority value corresponding to the first instruction;
• and
• issuing, in dependence upon the priority value for the first instruction having a higher priority than a priority value for another instruction, the first instruction to an execution unit of the computer processor.

An apparatus comprising:

• a computer processor and an instruction sequencing unit, wherein the computer processor is configured to carry out:
• receiving, from an instruction fetch unit of the computer processor, a first instruction and a branch instruction;
• responsive to determining that the branch instruction is dependent upon a result of the first instruction, updating a priority value corresponding to the first instruction;
• and
• issuing, in dependence upon the priority value for the first instruction having a higher priority than a priority value for another instruction, the first instruction to an execution unit of the computer processor.