System and Method for Tracing Data Addresses

A method, comprising, in a processor:

• receiving a first instruction in an instruction stream;
• decoding the first instruction;
• executing the first instruction, including:
• determining that a value of a first register input to an address generation operation for a memory access performed by the first instruction is not predictable in an instruction simulation of the plurality of instructions;
• retiring the first instruction, including:
• outputting, in response to determining that the value of the first register is not predictable in the instruction simulation, the value of the first register to a trace of the execution of the plurality of instructions.

A system, comprising:

• a front end to receive a plurality of instructions;
• a decoder to decode the plurality of instructions;
• a core to execute the plurality of instructions, including circuitry to:
• determine, during execution of a first instruction of the plurality of instructions, whether or not a value of a first register input to an address generation operation for a memory access performed by the first instruction is predictable in an instruction simulation of the plurality of instructions;
• a retirement unit to retire the plurality of instructions;
• and
• a trace unit, including circuitry to:
• output, during retirement of the first instruction, responsive to a determination that the value of the first register is not predictable in the instruction simulation, the value of the first register to a trace of the execution of the plurality of instructions;
• elide the output of the value of the first register to the trace of the execution of the plurality of instructions, responsive to a determination that the value of the first register is predictable in the instruction simulation.