Systems, apparatuses, and methods for snooping persistent memory store addresses
AssigneeIntel Corporation
InventorSara Baghsorkhi
Life of this patent
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Abstract
Systems, methods, and apparatuses for executing an instruction are described. In some embodiments, a decoder circuit decodes an instruction, wherein the instruction to include at least an opcode, a field for source operand, and a field for a destination operand. Execution circuitry executes the decoded instruction to determine if a tag from the address from the source operand matches a tag in a selected non-volatile memory address cache (NVMAC) cache line, wherein when there is a match a hit indication is stored in the destination operand, and when there is not a match, a no hit indication is stored in the destination operand and the NVMAC is updated with the tag from the address from the source operand.
Claims20
An apparatus comprising:
- a decoder circuit to decode an instruction, wherein the instruction to include at least an opcode, a field for source operand, and a field for a destination operand;
- and
- execution circuitry to execute the decoded instruction to determine if a tag from the address from the source operand matches a tag in a selected non-volatile memory address cache (NVMAC) cache line, wherein when there is a match a hit indication is stored in the destination operand, and when there is not a match, a no hit indication is stored in the destination operand and the NVMAC is updated with the tag from the address from the source operand.
A method comprising:
- decoding an instruction, wherein the instruction to include at least an opcode, a field for source operand, and a field for a destination operand;
- and
- executing the decoded instruction to determine if a tag from the address from the source operand matches a tag in a selected non-volatile memory address cache (NVMAC) cache line, wherein when there is a match a hit indication is stored in the destination operand, and when there is not a match, a no hit indication is stored in the destination operand and the NVMAC is updated with the tag from the address from the source operand.
A non-transitory machine-readable medium storing instructions which when executed to cause a processor to:
- decode an instruction, wherein the instruction to include at least an opcode, a field for source operand, and a field for a destination operand;
- and
- execute the decoded instruction to determine if a tag from the address from the source operand matches a tag in a selected non-volatile memory address cache (NVMAC) cache line, wherein when there is a match a hit indication is stored in the destination operand, and when there is not a match, a no hit indication is stored in the destination operand and the NVMAC is updated with the tag from the address from the source operand.
Dependencies are inferred from the claim text.