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US 2018/0004522 A1Published application
Apparatuses, methods, and systems for memory disambiguation
AssigneeIntel Corporation
InventorsVIKASH AGARWAL, CHRISTOPHER D. BRYANT, JONATHAN D. COMBS, STEPHEN J. ROBINSON
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Abstract
Apparatuses, methods, and systems relating to memory disambiguation are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, an execution unit to execute the decoded instruction, a retirement unit to retire an executed instruction in program order, and a memory disambiguation circuit to allocate an entry in a memory disambiguation table for a first load instruction that is to be flushed for a memory ordering violation, the entry comprising a counter value and an instruction pointer for the first load instruction.
Claims24
A processor comprising:
- a decoder to decode an instruction into a decoded instruction;
- an execution unit to execute the decoded instruction;
- a retirement unit to retire an executed instruction in program order;
- and
- a memory disambiguation circuit to allocate an entry in a memory disambiguation table for a first load instruction that is to be flushed for a memory ordering violation, the entry comprising a counter value and an instruction pointer for the first load instruction,
- wherein the memory disambiguation circuit is, for a second load instruction to be executed, to compare an instruction pointer for the second load instruction to the instruction pointer for the first load instruction and when there is a match and the counter value exceeds a threshold value, to prevent the second load instruction from bypassing an older store instruction without an access address, and wherein after the second load instruction is executed, the memory disambiguation circuit is to increment the counter value when the second load instruction bypassed an older store instruction that is to write data that the second load instruction is to consume, and decrement the counter value when the second load instruction bypassed an older store instruction that is not to write data that the second load instruction is to consume.
3 more elements
A method comprising:
- decoding an instruction into a decoded instruction with a decoder of a processor;
- executing the decoded instruction with an execution unit of the processor;
- retiring an executed instruction in program order with a retirement unit of the processor;
- allocating, with a memory disambiguation circuit, an entry in a memory disambiguation table for a first load instruction that is to be flushed for a memory ordering violation, the entry comprising a counter value and an instruction pointer for the first load instruction;
- and
- comparing, with the memory disambiguation circuit for a second load instruction to be executed, an instruction pointer for the second load instruction to the instruction pointer for the first load instruction and when there is a match and the counter value exceeds a threshold value, preventing the second load instruction from bypassing an older store instruction without an access address, and wherein after the second load instruction is executed, the memory disambiguation circuit is to increment the counter value when the second load instruction bypassed an older store instruction that is to write data that the second load instruction is to consume, and decrement the counter value when the second load instruction bypassed an older store instruction that is not to write data that the second load instruction is to consume.
3 more elements
A processor comprising:
- a decoder to decode an instruction into a decoded instruction;
- an execution unit to execute the decoded instruction;
- a retirement unit to retire an executed instruction in program order;
- and
- a memory disambiguation circuit to allocate a first entry in a memory disambiguation table for a single load and store pair of instructions that are to be flushed for a memory ordering violation, the first entry comprising a counter value and an instruction pointer for a load instruction of the single load and store pair of instructions, and allocate a second entry in the memory disambiguation table for multiple load instructions and a single store instruction that are to be flushed for a memory ordering violation, the second entry comprising a counter value and an instruction pointer for the single store instruction.
2 more elements
A method comprising:
- decoding an instruction into a decoded instruction with a decoder of a processor;
- executing the decoded instruction with an execution unit of the processor;
- retiring an executed instruction in program order with a retirement unit of the processor;
- and
- allocating, with a memory disambiguation circuit, a first entry in a memory disambiguation table for a single load and store pair of instructions that are to be flushed for a memory ordering violation, the first entry comprising a counter value and an instruction pointer for a load instruction of the single load and store pair of instructions, and allocate a second entry in the memory disambiguation table for multiple load instructions and a single store instruction that are to be flushed for a memory ordering violation, the second entry comprising a counter value and an instruction pointer for the single store instruction.
2 more elements
Dependencies are inferred from the claim text.