Processors, methods, and systems to identify stores that cause remote transactional execution aborts

A processor comprising:

• a first logical processor, the first logical processor including:
• transactional execution logic to start a transactional execution transaction;
• a second logical processor to perform store to memory instructions, including a first store to memory instruction to a first memory address, while the transactional execution transaction is to be performed by the first logical processor;
• and
• a performance monitor unit to:
• capture memory addresses of, and instruction pointer values associated with, at least a sample of the store to memory instructions;
• and
• capture the first memory address, when the first memory address is to cause the transaction to abort.

A computer system comprising:

• a processor, the processor comprising:
• a first logical processor, the first logical processor including:
• transactional execution logic to start a transactional execution transaction;
• a second logical processor to perform store to memory instructions, including a first store to memory instruction to a first memory address, while the transactional execution transaction is to be performed by the first logical processor;
• and
• a performance monitor unit to:
• capture memory addresses of, and instruction pointer values associated with, at least a sample of the store to memory instructions;
• and
• capture the first memory address, when the first memory address is to cause the transaction to abort;
• and
• a dynamic random access memory coupled with the processor, the dynamic random access memory storing a set of instructions, the set of instructions, if executed by the computer system, to cause the computer system to perform operations comprising determining an instruction pointer value associated with the first store to memory instruction by correlating at least the captured first memory address with the captured memory addresses of said at least the sample of the store to memory instructions.

An article of manufacture comprising a non-transitory machine-readable storage medium, the non-transitory machine-readable storage medium storing a set of instructions, the set of instructions, if executed by a machine, to cause the machine to perform operations comprising:

• accessing memory addresses of, and instruction pointer values associated with, at least a sample of store to memory instructions, which are to have been performed by a second logical processor while a transactional execution transaction was being performed with a first logical processor;
• accessing a first memory address associated with a first store to memory instruction, which is to have caused an abort of the transactional execution transaction;
• and
• determining an instruction pointer value associated with the first store to memory instruction by correlating at least the first memory address with the memory addresses of said at least the sample of the store to memory instructions.