Sort acceleration processors, methods, systems, and instructions

A method in a processor comprising:

• receiving an instruction, the instruction indicating a first source packed data including a first set of at least four data elements, indicating a second source packed data including a second set of at least four data elements, and indicating a destination storage location;
• and
• storing result packed data in the destination storage location in response to the instruction, the result packed data including,
• at least four indexes,
• the indexes identifying corresponding data element positions in the first and second source packed data, and
• the indexes stored in positions in the result packed data that represent a sorted order of corresponding data elements in the first and second source packed data.

A processor comprising:

• a plurality of packed data registers;
• a decode unit to decode an instruction, the instruction to indicate a source packed data that is to include at least four data elements that are not in a sorted order, and to indicate a destination storage location;
• an execution unit coupled with the packed data registers and the decode unit, the execution unit, in response to the instruction, to store a result packed data in the destination storage location,
• the result packed data to include at least four indexes,
• the indexes to identify corresponding data elements in the source packed data, and
• the indexes to be stored in positions in the result packed data that are to represent the sorted order of the corresponding data elements in the source packed data.