Processor and control method of processor

A control method of a processor, the control method comprising:

• decoding an instruction by a decoding unit of the processor;
• when the instruction decoded by the decoding unit is an instruction to execute arithmetic processing on a plurality of operand sets each including a plurality of operands that are objects of the arithmetic processing, in parallel a plurality of times, generating, by an address generating unit of the processor, an address set corresponding to each of the operand sets of the arithmetic processing for each time, based on a certain address displacement with respect to the plurality of operands included in each of the operand sets;
• holding, by a plurality of address holding units of the processor, the address sets corresponding to the respective operand sets, that are generated by the address generating unit, in correspondence to respective processing units;
• and
• performing, by a plurality of processing units of the processor, the arithmetic processing in parallel on the respective operand sets obtained based on the address sets outputted by the plurality of address holding units.