US 2018/0004512 A1Published application

System and Method for Out-of-Order Clustered Decoding

AssigneeIntel Corporation

InventorJonathan D. Combs

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Abstract

A processor includes a core to execute decoded instructions and a front end. The front end includes two decode clusters and circuitry to receive data elements representing undecoded instructions, in program order, and to direct different subsets of the data elements to the two decode clusters. A splitter begins directing data elements to the first decode cluster, detects a cluster switching trigger condition, and directs a second subset of the data elements that immediately follows the first subset of data elements in program order to the second decode cluster. The trigger condition may be a predicated taken branch. The front end also includes circuitry to merge the decoded instructions generated by the first decode cluster and the decoded instructions generated by the second decode cluster to generate a sequence of decoded instructions in program order, based on a toggle indicator, and to provide it to the core for execution.

Claims20

Dependent claims

A system, comprising:

a core to execute decoded instructions;
a front end including:
a first decode cluster;
a second decode cluster;
a first output queue;
a second output queue;
circuitry to receive a plurality of data elements, each to represent an undecoded instruction in an ordered sequence of undecoded instructions of a program in program order;
a splitter including circuitry to:
direct a first subset of the plurality of data elements to the first decode cluster, the data elements in the first subset of data elements to be in program order, and the first decode cluster including circuitry to:
decode the first subset of data elements;
and
store decode results as decoded instructions in the first output queue;
detect that a trigger condition for a cluster switch has been met;
direct, responsive to the detection, a second subset of the plurality of data elements that immediately follows the first subset of data elements in program order to the second decode cluster, the data elements in the second subset of data elements to be in program order, and the second decode cluster including circuitry to:
decode the second subset of data elements;
and
store decode results as decoded instructions in the second output queue;
a combiner including circuitry to:
merge at least a subset of the decoded instructions stored in the first output queue and at least a subset of the decoded instructions stored in the second output queue to generate a sequence of decoded instructions in program order;
provide the sequence of decoded instructions to the core for execution.

17 more elements

A method, comprising, in a processor:

receiving a stream of data elements, each representing an undecoded instruction in an ordered sequence of undecoded instructions of a program in program order;
directing a first subset of the plurality of data elements to a first decode cluster, the data elements in the first subset of data elements being in program order;
detecting that a trigger condition for a cluster switch has been met;
directing, in response to the detecting, a second subset of the plurality of data elements that immediately follows the first subset of data elements in program order to a second decode cluster, the data elements in the second subset of data elements being in program order;
decoding, by the first decode cluster, the first subset of data elements to produce a first collection of decoded instructions;
decoding, by the second decode cluster, the second subset of data elements to produce a second collection of decoded instructions;
merging at least a portion of the first collection of decoded instructions and at least a portion of the second collection of decoded instructions to generate a sequence of decoded instructions in program order;
providing the sequence of decoded instructions to a core for execution.

5 more elements

A processor, comprising:

a core to execute decoded instructions;
a front end including:
a first decode cluster;
a second decode cluster;
a first output queue;
a second output queue;
circuitry to receive a plurality of data elements, each to represent an undecoded instruction in an ordered sequence of undecoded instructions of a program in program order;
a splitter including circuitry to:
direct a first subset of the plurality of data elements to the first decode cluster, the data elements in the first subset of data elements to be in program order, and the first decode cluster including circuitry to:
decode the first subset of data elements;
and
store decode results as decoded instructions in the first output queue;
detect that a trigger condition for a cluster switch has been met;
direct, responsive to the detection, a second subset of the plurality of data elements that immediately follows the first subset of data elements in program order to the second decode cluster, the data elements in the second subset of data elements to be in program order, and the second decode cluster including circuitry to:
decode the second subset of data elements;
and
store decode results as decoded instructions in the second output queue;
a combiner including circuitry to:
merge at least a subset of the decoded instructions stored in the first output queue and at least a subset of the decoded instructions stored in the second output queue to generate a sequence of decoded instructions in program order;
provide the sequence of decoded instructions to the core for execution.

17 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/198,856Filed 30 Jun 2016
Published: 4 Jan 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 9/3016
Instruction analysis, e.g. decoding, instruction word fields: decoding the operand specifier, e.g. specifier format
G06F 9/30145
Arrangements for executing machine instructions, e.g. instruction decode: instruction analysis, e.g. decoding, instruction word fields
G06F 9/30149
Instruction analysis, e.g. decoding, instruction word fields: of variable length instructions
G06F 9/30152
Of variable length instructions: determining start or end of instruction; determining instruction length