Technologies for optimizing sparse matrix code with field-programmable gate arrays

One or more computer-readable storage media comprising a plurality of instructions that in response to being executed cause a computing device to:

• identify a performance-critical loop in a sparse matrix source code;
• and
• generate optimized executable code for the sparse matrix source code, wherein the optimized executable code includes processor code and field-programmable gate array (FPGA) code, wherein:
• the processor code is to cause a processor of a target computing device to (i) execute a first iteration of the performance-critical loop and (ii) generate reusable optimization data of the performance-critical loop in response to execution of the first iteration;
• and
• the FPGA code is to cause an FPGA of the target computing device to (i) execute one or more additional iterations of the performance-critical loop and (ii) optimize the one or more additional iterations of the loop based on the reusable optimization data.

A computing device for optimizing sparse matrix code, the computing device comprising:

• a processor;
• a field-programmable gate array (FPGA);
• a processor code module to (i) execute, by the processor, a first iteration of a loop of a sparse matrix executable code, (ii) generate, by the processor, reusable optimization data of the loop in response to execution of the first iteration of the loop, and (iii) store, by the processor, the reusable optimization data in a shared memory of the computing device;
• and
• an FPGA code module to (i) access, by the FPGA, the reusable optimization data in the shared memory of the computing device, (ii) execute, by the FPGA, one or more additional iterations of the loop of the sparse matrix executable code, and (iii) optimize, by the FPGA, the one or more additional iterations of the loop based on the reusable optimization data in response to accessing of the reusable optimization data.

One or more computer-readable storage media comprising a plurality of instructions that in response to being executed cause a computing device to:

• execute, by a processor of the computing device, a first iteration of a loop of a sparse matrix executable code;
• generate, by the processor of the computing device, reusable optimization data of the loop in response to executing the first iteration of the loop;
• store, by the processor of the computing device, the reusable optimization data in a shared memory of the computing device;
• access, by a field-programmable gate array (FPGA) of the computing device, the reusable optimization data in the shared memory of the computing device;
• execute, by the FPGA of the computing device, one or more additional iterations of the loop of the sparse matrix executable code;
• and
• optimize, by the FPGA of the computing device, the one or more additional iterations of the loop based on the reusable optimization data in response to accessing the reusable optimization data.