Engine architecture for processing finite automata

A hyper non-deterministic finite automata (HNA) processor specialized for non-deterministic finite automata (NFA) processing, the HNA processor comprising:

• a plurality of clusters, each cluster of the plurality of clusters including a plurality of HNA processing units (HPUs);
• and
• an HNA on-chip instruction queue configured to store at least one HNA instruction, the plurality of HPUs of the plurality of clusters forming a resource pool of HPUs available for assignment of the at least one HNA instruction;
• and
• an HNA scheduler configured to select a given HPU of the resource pool formed and assign the at least one HNA instruction to the given HPU selected in order to initiate matching at least one regular expression pattern in an input stream received from a network.

A method comprising:

• including a plurality of clusters in at least one hyper non-deterministic automata (HNA) processor specialized for non-deterministic finite automata (NFA) processing, each cluster of the plurality of clusters including a plurality of HNA processing units (HPUs);
• storing at least one HNA instruction in an HNA on-chip instruction queue;
• and
• selecting, by an HNA scheduler, a given HPU of the plurality of HPUs of the plurality of clusters and assigning the at least one HNA instruction to the given HPU selected in order to initiate matching at least one regular expression pattern in an input stream received from a network.