Memory controller, memory buffer chip and memory system

A memory buffer chip which is positioned between a memory controller and one or more memory chips, comprising:

• a first interface configured to transmit and receive a signal to and from the memory controller;
• a second interface configured to transmit and receive a signal to and from the memory chip;
• a command buffer configured to buffer commands received from the memory controller through the first interface;
• and
• a read buffer configured to buffer read data received from the memory chip,
• wherein based on a first event occurring, the command buffer informs the memory controller of the first event through the first interface, and
• wherein the first event includes transmitting one of the commands stored in the command buffer to the memory chip through the second interface.

A memory system comprising:

• a memory buffer chip coupled to one or two or more memory chips;
• and
• a memory controller configured to control the memory buffer chip to input and output data to and from the one or more memory chips,
• wherein the memory buffer chip comprises:
• a first interface configured to transmit and receive a signal to and from the memory controller;
• a second interface configured to transmit and receive a signal to and from the memory chip;
• a command buffer configured to buffer commands received from the memory controller through the first interface;
• and
• a read buffer configured to buffer read data received from the memory chip, and
• wherein the memory controller outputs a command to the memory buffer chip based on the command buffer having a space for storage or the read buffer storing data.