Enhanced address space layout randomization
AssigneeIntel Corporation
InventorsTOMER STARK, RON GABOR, JOSEPH NUZMAN
Life of this patent
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Abstract
One embodiment provides an apparatus. The apparatus includes a linear address space, metadata logic and enhanced address space layout randomization (ASLR) logic. The linear address space includes a metadata data structure. The metadata logic is to generate a metadata value. The enhanced ASLR logic is to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address. The address pointer corresponds to an apparent address in an enhanced address space. A size of the enhanced address space is greater than a size of the linear address space.
Claims25
An enhanced address space layout randomization apparatus comprising:
- a linear address space comprising a metadata data structure;
- metadata logic to generate a metadata value;
- and
- enhanced address space layout randomization (ASLR) logic to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address,
- the address pointer corresponding to an apparent address in an enhanced address space, a size of the enhanced address space greater than a size of the linear address space.
An enhanced address space layout randomization method comprising:
- generating, by metadata logic, a metadata value;
- combining, by enhanced address space layout randomization (ASLR) logic, the metadata value and a linear address into an address pointer;
- and
- storing, by the enhanced ASLR logic, the metadata value to a metadata data structure at a location pointed to by a least a portion of the linear address,
- the metadata data structure included in a linear address space, the address pointer corresponding to an apparent address in an enhanced address space, a size of the enhanced address space greater than a size of the linear address space.
An enhanced address space layout randomization system comprising:
- a processor comprising at least one processor register;
- a linear address space comprising a metadata data structure;
- metadata logic to generate a metadata value;
- and
- enhanced address space layout randomization (ASLR) logic to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address,
- the address pointer corresponding to an apparent address in an enhanced address space, a size of the enhanced address space greater than a size of the linear address space.
A computer readable storage device having stored thereon instructions that when executed by one or more processors result in the following operations comprising:
- generating a metadata value;
- combining the metadata value and a linear address into an address pointer;
- and
- storing the metadata value to a metadata data structure at a location pointed to by a least a portion of the linear address,
- the metadata data structure included in a linear address space, the address pointer corresponding to an apparent address in an enhanced address space, a size of the enhanced address space greater than a size of the linear address space.
Dependencies are inferred from the claim text.