Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device

A system, comprising:

• a processor having a cache manager;
• a main memory for the processor including a first level memory device and a second level memory device, wherein the first level memory device caches data for the second level memory device, and wherein the first level memory device has a non-power of 2 cache size to cache data present in the second level memory device having a 2n size larger than the non-power of 2 cache size of the first level memory device;
• and
• a cache manager to:
• receive a request to a target address having n bits directed to the second level memory device;
• determine whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device, wherein an index set of 2m is greater in size than the index set in the first level memory device;
• determine a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index;
• and
• process the request with respect to data in a cache line at the modified target index in the first level memory device.

A method, comprising:

• caching in a first level memory device, comprising a non-power of 2 cache size, data present in a second level memory device having a 2n size larger than the non-power of 2 cache size of the first level memory device;
• receiving a request to a target address having n bits directed to the second level memory device;
• determining whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device, wherein an index set of 2m is greater in size than the index set in the first level memory device;
• determining a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index;
• and
• processing the request with respect to data in a cache line at the modified target index in the first level memory device.