Memory device for high speed data transfer
AssigneeSK hynix Inc.
InventorKyeong Min CHAE
Life of this patent
Estimating the term…
Abstract
A memory device may include a data output controller for generating a first clock signal and a second clock signal in response to a read enable clock signal, a page buffer for storing data, and outputting the data to the data output controller in synchronization with the first clock signal, and a data output buffer for receiving the data from the page buffer and outputting the received data to the external device in synchronization with the second clock signal. The first clock signal is generated in response to a data output delay control signal, the second clock signal is generated irrespective of the data output delay control signal.
Claims20
A memory device comprising:
- a data output controller configured to generate first and second clock signals in response to a read enable clock signal received from an external device during a data output operation;
- a page buffer configured to output data to the data output controller in synchronization with the first clock signal;
- and
- a data output buffer configured to receive the data from the page buffer and to output the received data to the external device in synchronization with the second clock signal,
- wherein the first clock signal is generated in response to a data output delay control signal,
- the second clock signal is generated irrespective of the data output delay control signal, and
- a time point of outputting the data to the external device is changed according to a set value of the data output delay control signal.
A memory device comprising:
- a data input buffer configured to receive a data strobe clock signal and data in synchronization with the data strobe clock signal from an external device during a data input operation, and to generate a first clock signal in response to the data strobe clock signal;
- a data input delay controller configured to receive the data output from the data input buffer in synchronization with the first clock signal, and to generate one or more second clock signals in response to the first clock signal and under a control by a data input delay signal;
- and
- a page buffer configured to receive the data from the data input delay controller, and to store the data in synchronization with the one or more second clock signals,
- wherein the first clock signal is generated irrespective of the data input delay signal.
Dependencies are inferred from the claim text.