Hierarchical flash translation layer structure and method for designing the same

A system for designing a Flash Translation Layer (FTL) including mapping information for storing data, the system comprising:

• a log developer for generating logs in a hierarchical structure in correspondence with respective hierarchical data groups of the FTL, for processing data of the corresponding data groups,
• a verifier for verifying the logs;
• a register for generating log components for logs verified by the verifier and registering the generated log components to a library;
• and
• a designer for designing the FTL by combining log components satisfying required conditions related to system performance and resource use amount for a target storage system from among the log components registered to the library,
• wherein each of the logs provides an interface to volatile memory resources dividedly allocated to the log, an interface to non-volatile memory resources dividedly allocated to the log, and an interface to at least one of a lower-layer log and a higher-layer log.