Method and circuit for dynamic power control

A multi-core processor, comprising:

• a first core, the first core having a first data processing pipeline configured to receive a first master clock signal and configured to perform a first operation triggered by a plurality of first timing edges of the first master clock signal;
• a second core, the second core having a second data processing pipeline configured to receive a second master clock signal and configured to perform a second operation triggered by a plurality of second timing edges of the second master clock signal;
• and
• a clock control circuit configured to supply the first master clock signal to the first core and the second master clock signal to the second core, wherein at least some of the clock edges of the first and second master clock signals are out of phase with each other.

A data processing pipeline circuit design method, comprising:

• modifying an initial circuit design of a data processing pipeline by splitting an initial pipeline stage into two parallel pipeline sub-stages, the two parallel pipeline sub-stages including:
• a first pipeline stage configured to perform a first operation triggered by first timing edges of a first clock signal;
• and
• a second pipeline stage configured to perform a second operation triggered by second timing edges of a second clock signal, the second clock signal independent of the first clock signal;
• and
• integrating the modified initial circuit design with a clock controller configured to generate the first and second clock signals, wherein the clock controller is arranged to operate:
• in a first mode in which, during a first data processing cycle of the data processing pipeline, a first of the first timing edges is in-phase with a first of the second timing edges;
• and
• in a second mode in which, during a second data processing cycle of the data processing pipeline, a second of the first timing edges is out of phase with a second of the second timing edges.

A method of dynamically controlling a data processing pipeline, comprising:

• generating, by a clock controller, first and second clock signals from a master clock signal;
• providing the first clock signal to a first pipeline stage configured to perform a first operation triggered by first timing edges of the first clock signal;
• providing the second clock signal to a second pipeline stage configured to perform a second operation triggered by second timing edges of the second clock signal;
• operating the clock controller in a first mode in which, during a first data processing cycle of the data processing pipeline, one or more of the first timing edges are in phase with one or more of the second timing edges;
• and
• operating the clock controller in a second mode in which, during a second data processing cycle of the data processing pipeline, one or more of the first timing edges are out of phase with respect to one or more of the second timing edges.