US 2018/0004246 A1 · Computer System

Abstract

A problem to be solved by the present invention is, in a computer system, to reduce processing delay from wait times which occur in timer access. According to the present invention, using either a CPU core (hereinafter “processing core”) other than a CPU core which executes an application, or a DMA device, a latest timer value is always transferred from a timer device to a primary storage device. The processing core reads the transferred value upon the primary storage device instead of accessing a register of the timer device, thereby avoiding a wait which occurs when directly reading the timer value of the timer device. The transfer of the value is carried out asynchronously from the processing of the processing core, thus obviating the need for the processing core to wait for the completion of the transfer. Accordingly, it is also unnecessary for the processing core to process an interrupt or a notification from another CPU core or the DMA device.

Claims4

Dependent claims

A computer system comprising a first processing unit, a second processing unit, a primary storage device, and a timer device, wherein

the timer device stores in the timer device timestamp information and includes a timestamp register accessible from the second processing unit,
the primary storage device includes a timestamp transfer buffer that stores in the primary storage device the timestamp information that the second processing unit read from the timestamp register of the timer device,
the first processing unit reads the timestamp information from the timestamp transfer buffer, and
the second processing unit stores the timestamp information in the timestamp transfer buffer at a different timing from the first processing unit reading the timestamp information.

1 more element

Dependencies are inferred from the claim text.

Computer System

Life of this patent

Computer System

Life of this patent

Abstract

Claims4