Low clock-energy 3-phase latch-based clocking scheme
AssigneeIntel Corporation
InventorsVikram B. Suresh, Sudhir K. Satpathy, Sanu K. Mathew
Life of this patent
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Abstract
A processing system includes a processor and a hardware accelerator, communicatively coupled to the processor, comprising a plurality of circuits to perform a plurality rounds of computation, wherein the plurality of circuits comprise a first set of level-sensitive latches enabled by a first clock signal to store data associated with a first round of the plurality of rounds of computation and a second set of level-sensitive latches enabled by a second clock signal to store data associated with a second round of the plurality of rounds of computation, and wherein a duty cycle of the first clock signal and a duty cycle of the second clock signal are non-overlapping.
Claims21
A processing system comprising:
- a processor;
- and
- a hardware accelerator, communicatively coupled to the processor, comprising a plurality of circuits to perform a plurality rounds of computation, wherein the plurality of circuits comprise a first set of level-sensitive latches enabled by a first clock signal to store data associated with a first round of the plurality of rounds of computation and a second set of level-sensitive latches enabled by a second clock signal to store data associated with a second round of the plurality of rounds of computation, and wherein a duty cycle of the first clock signal and a duty cycle of the second clock signal are non-overlapping.
An application specific integrated circuit (ASIC) comprising:
- a plurality of circuits to perform a plurality rounds of computation, wherein the plurality of circuits comprise a first set of level-sensitive latches enabled by a first clock signal to store data associated with a first round of the plurality of rounds of computation and a second set of level-sensitive latches enabled by a second clock signal to store data associated with a second round of the plurality of rounds of computation, and wherein a duty cycle of the first clock signal and a duty cycle of the second clock signal are non-overlapping.
A method comprising:
- performing a first round of a plurality of rounds of computation by employing a first set of level-sensitive latches enabled by a first clock signal;
- performing a second round of the plurality of rounds of computation by employing a second set of level-sensitive latches enabled by a second clock signal;
- and
- performing a third round of the plurality of rounds of computation by employing a third set of level-sensitive latches enabled by a third clock signal, wherein the first clock signal, the second clock signal, and the third clock signal are generated from a system clock.
Dependencies are inferred from the claim text.