Diagnosing failure locations of an integrated circuit with logic built-in self-test
AssigneeGlobalfoundries Inc.
InventorsSTEVEN M. DOUSKEY, AMANDA R. KAUFER, LEAH MARIE PFEIFER PASTEL
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AssigneeGlobalfoundries Inc.
InventorsSTEVEN M. DOUSKEY, AMANDA R. KAUFER, LEAH MARIE PFEIFER PASTEL
Estimating the term…
A method and system of testing an integrated circuit (IC), using a multiple input shift register (MISR) with supporting hardware for diagnosing failure locations in an IC with built-in self-test (BIST) logic, including an On-Product MISR. The system includes BIST logic of a circuit under test (CUT) and a tester including an isolation hatch table (IHT) that translates signature fail data of the MISR to a failure location of a latch in the CUT. Signature fail data, and consequently, failure locations in the CUT, are obtained by standard testing of the CUT, testing of selected single channels of the CUT, and data insertion functions to the selected single channels of the CUT to obtain compressed MISR signature changes that, when translated, provide failure locations in the CUT.
A system comprising:
A method comprising:
A method comprising:
Dependencies are inferred from the claim text.