Phase frequency detection device

A phase frequency detection device comprising:

• filter circuitry including a plurality of transversal filters which are connected in parallel to each other, the plurality of transversal filters changing amplitude and a phase of an input digital signal and outputting different digital signals as respective resulting digital signals whose amplitude and phase have been changed;
• and
• a phase frequency computer to compute a phase and a frequency of the input digital signal by performing phase computation and frequency computation using the digital signals output by the plurality of transversal filters,
• wherein
• the filter circuitry is constituted such that a first transversal filter, a second transversal filter, and a third transversal filter, as the plurality of transversal filters, are connected in parallel to each other, and
• the phase frequency computer includes:
• first division computation circuitry to perform a division computation between a digital signal output by the first transversal filter and a digital signal output by the second transversal filter, and to output a first division computation signal being a result of the division computation;
• second division computation circuitry to perform a division computation between a digital signal output by the third transversal filter and the digital signal output by the second transversal filter, and to output a second division computation signal being a result of the division computation;
• multiplication computation circuitry to perform a multiplication computation between the first division computation signal output by the first division computation circuitry and the second division computation signal output by the second division computation circuitry, and to output a multiplication computation signal being a result of the multiplication computation;
• root computation circuitry to perform a root computation on the multiplication computation signal output by the multiplication computation circuitry, and to output a root computation signal being a result of the root computation;
• phase computation circuitry to compute a phase of the input digital signal by using the root computation signal output by the root computation circuitry and a sign of the first division computation signal or the second division computation signal;
• and
• frequency computation circuitry to compute a frequency of the input digital signal by using the phase computed by the phase computation circuitry.

A phase frequency detection device comprising:

• filter circuitry including a plurality of transversal filters which are connected in parallel to each other, the plurality of transversal filters changing amplitude and a phase of an input digital signal and outputting different digital signals as respective resulting digital signals whose amplitude and phase have been changed;
• and
• A phase frequency computer to compute a phase and a frequency of the input digital signal by performing phase computation and frequency computation using the digital signals output by the plurality of transversal filters,
• wherein
• the filter circuitry is constituted such that a first transversal filter, a second transversal filter, and a third transversal filter, as the plurality of transversal filters, are connected in parallel to each other, and
• the phase frequency computer includes:
• first multiplication computation circuitry to perform a multiplication computation between a digital signal output by the first transversal filter and a digital signal output by the third transversal filter, and to output a first multiplication computation signal being a result of the multiplication computation;
• second multiplication computation circuitry to perform a square multiplication on a digital signal output by the second transversal filter, and to output a second multiplication computation signal being a result of the square multiplication;
• division computation circuitry to perform a division computation between the first multiplication computation signal output by the first multiplication computation circuitry and the second multiplication computation signal output by the second multiplication computation circuitry, and to output a division computation signal being a result of the division computation;
• root computation circuitry to perform a root computation on the division computation signal output by the division computation circuitry, and to output a root computation signal being a result of the root computation;
• phase computation circuitry to compute a phase of the input digital signal by using the root computation signal output by the root computation circuitry and a sign of the first multiplication computation signal;
• and
• frequency computation circuitry to compute a frequency of the input digital signal by using the phase computed by the phase computation circuitry.

A phase frequency detection device comprising:

• filter circuitry including a plurality of transversal filters which are connected in parallel to each other, the plurality of transversal filters changing amplitude and a phase of an input digital signal and outputting different digital signals as respective resulting digital signals whose amplitude and phase have been changed;
• and
• a phase frequency computer to compute a phase and a frequency of the input digital signal by performing phase computation and frequency computation using the digital signals output by the plurality of transversal filters,
• wherein
• the filter circuitry is constituted such that a first transversal filter and a second transversal filter, as the plurality of transversal filters, are connected in parallel to each other, and
• the phase frequency computer includes:
• division computation circuitry to perform a division computation between a digital signal output by the first transversal filter and a digital signal output by the second transversal filter, and to output a division computation signal being a result of the division computation;
• root computation circuitry to perform a root computation on the division computation signal output by the division computation circuitry, and to output a root computation signal being a result of the root computation;
• frequency computation circuitry to compute a frequency of the input digital signal by using the root computation signal output by the root computation circuitry;
• and
• phase computation circuitry for computing a phase of the input digital signal by using the frequency computed by the frequency computation circuitry.

A phase frequency detection device comprising:

• filter circuitry including a plurality of transversal filters which are connected in parallel to each other, the plurality of transversal filters changing amplitude and a phase of an input digital signal and outputting different digital signals as respective resulting digital signals whose amplitude and phase have been changed;
• and
• a phase frequency computer to compute a phase and a frequency of the input digital signal by performing phase computation and frequency computation using the digital signals output by the plurality of transversal filters,
• wherein
• each of the plurality of transversal filters is constituted by
• one or more subtraction-type first-order transversal filters connected in series with each other or
• one or more addition-type first-order transversal filters connected in series with each other or
• a subtraction-type first-order transversal filter and an addition-type first-order transversal filter, which are connected in series with each other,
• each of the subtraction-type first-order transversal filters is constituted by:
• first splitter circuitry to split an input digital signal;
• first delaying circuitry to delay one digital signal split by the first splitter circuitry by one sampling time;
• and
• subtraction computation circuitry to perform a subtraction computation between the digital signal delayed by the first delaying circuitry and the other digital signal split by the first splitter circuitry, and
• each of the addition-type first-order transversal filters is constituted by:
• second splitter circuitry to split an input digital signal;
• second delaying circuitry to delay one digital signal split by the second splitter circuitry (61) by one sampling time;
• and
• addition computation circuitry to perform an addition computation between the digital signal delayed by the second delaying circuitry and the other digital signal split by the second splitter circuitry.