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US 2018/0000333 A1Published application
Pixel array area optimization using stacking scheme for hybrid image sensor with minimal vertical interconnects
AssigneeDePuy Synthes Products, Inc.
InventorLaurent Blanquart
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Abstract
Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.
Claims21
1-62. (canceled)
An imaging sensor comprising:
- a plurality of substrates comprising at least a first substrate and a second substrate;
- a pixel array located on the first substrate and comprising a plurality of pixel columns;
- a plurality of supporting circuits located on the second substrate and comprising a plurality of circuit columns, wherein each of the plurality of circuit columns is defined as having an area that corresponds with an area of a corresponding pixel column;
- a plurality of pixel column buses and a plurality of circuit column buses, wherein there is one pixel column bus per pixel column residing on the first substrate and one circuit column bus per circuit column residing on said second substrate;
- wherein at least one interconnect provides an electrical communication between one pixel column bus and one corresponding circuit column bus;
- and
- wherein said at least one interconnect is located anywhere between one pixel column bus and one corresponding circuit column bus.
4 more elements
An imaging sensor comprising:
- a plurality of substrates comprising a first substrate and a second substrate;
- a pixel array located on the first substrate comprising a plurality of pixel columns;
- and
- a plurality of supporting circuits comprising a plurality of circuit columns located on the second substrate, wherein said plurality of supporting circuits are electrically connected to said pixel array;
- a plurality of pixel column buses located on the first substrate and a plurality of circuit column buses located on the second substrate, wherein there is one pixel column bus per pixel column residing on the first substrate and one circuit column bus per circuit column residing on said second, subsequent supporting substrate;
- and
- wherein at least one interconnect electronically connects each of the pixel column buses to each of the corresponding circuit column buses.
4 more elements
Dependencies are inferred from the claim text.