Sampling clock generating circuit and analog to digital converter

An analog to digital converter (ADC), comprising:

• n ADC chips;
• a mixer connected to the n ADC chips;
• a sampling clock generating circuit connected to the mixer and comprising,
• a resistance variable circuit,
• a NOT-gate type circuit comprising an input end, an output end, a power supply terminal, and a ground terminal,
• a capacitor, and
• wherein the input end of the NOT-gate type circuit is configured to receive a pulse signal whose period is T, the output end of the NOT-gate type circuit is connected to one end of the capacitor, the other end of the capacitor is grounded, the power supply terminal of the NOT-gate type circuit is connected to a power supply, the ground terminal of the NOT-gate type circuit is connected to one end of the resistance variable circuit, and the other end of the resistance variable circuit is grounded;
• wherein the NOT-gate type circuit is configured to:
• when the pulse signal is a high level, output a low level, and when the pulse signal is a low level, output a high level;
• wherein the resistance variable circuit is configured to change a resistance value at intervals of duration T, wherein the resistance value is changed based on a period of n*T, and resistance values after changes within each period are different from each other, wherein n≧2 and n is an integer;
• wherein the mixer is configured to generate n channels of sampling signals whose periods are n*T, wherein within each period n*T, an level of an ith channel of sampling signal is the same as an level of an output signal of the sampling clock generating circuit within an (i-1)th time segment whose duration is T and is a low level within other time segments;
• and
• wherein an ith ADC chip is configured to use the ith channel of sampling signals as a sampling clock.