Thin film transistor array panel and manufacturing method of the same

A thin film transistor array panel, comprising:

• a baseplate;
• a data line, being formed by a first metal layer, wherein the first metal layer is disposed on the baseplate;
• a thin film transistors, the thin film transistor comprising:
• a source electrode, comprising a first block and a second block, the first block and the second block overlapping to combine integrally, the first block being a portion of the first metal layer located in a first region, the second block being a portion of a second metal layer located in the first region, wherein the first region is a portion to which the source electrode corresponds, the second metal layer disposed on the first metal layer, the source electrode connects with the data line;
• a drain electrode, which comprising a third block and a fourth block, the third block and the fourth block overlapping to combine integrally, the third block being a portion of the first metal layer located in a second region, the fourth block being a portion of a second metal layer located in the second region, wherein the second region is a portion to which the drain electrode corresponds, the second metal layer disposed on the first metal layer;
• a semiconductor layer, being overlapping on the source electrode, the drain electrode, and a gap between the source electrode and the drain electrode;
• a gate electrode, being over the semiconductor;
• an insulation layer, being overlapping on the data line and the semiconductor layer;
• a scanning line, being disposed on the insulation layer, the scanning line connecting with the gate electrode;
• a protection layer, being disposed on the scanning line and the insulation layer;
• an electrode layer, being formed by the first metal layer, the electrode layer connecting with the drain electrode;
• wherein the gate electrode is disposed on the insulation layer;
• the data line, the first block of the source electrode, the third block of the drain electrode, and the electrode layer are all formed by applying a first tone-mask process and a first etching process to the first metal layer;
• the second block of the source electrode and the fourth block of the drain electrode are both formed by applying a second etching process to the second metal layer which has been processed by the first tone-mask process and the first etching process;
• the semiconductor layer is formed by disposing a semiconductor material on at least one portion of the source electrode, at least one portion of the drain electrode, and the gap, then applying a second tone-mask process to the semiconductor material.