FinFETs with Strained Well Regions

A device comprising:

• a silicon substrate;
• insulation regions extending into the silicon substrate;
• a first silicon germanium region between the insulation regions and having a first germanium percentage, the first silicon germanium region comprises:
• a first sub layer having a first p-type impurity concentration;
• a second sub layer over and contacting the first sub layer, the second sub layer has a second p-type impurity concentration;
• and
• a third sub layer over and contacting the second sub layer, the third sub layer has a third p-type impurity concentration, wherein the second p-type impurity concentration is higher than both the first p-type impurity concentration and the third p-type impurity concentration;
• a second silicon germanium region over and adjoining the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage;
• and
• a silicon-containing cap adjoining a top surface and sidewalls of the second silicon germanium region, wherein the silicon-containing cap has a third germanium percentage lower than the second germanium percentage.

A device comprising:

• a silicon germanium region having a first germanium percentage, the silicon germanium region comprises:
• a first sub layer;
• a second sub layer over and contacting the first sub layer, the second sub layer is doped with a p-type impurity;
• and
• a third sub layer over and contacting the second sub layer, wherein the first sub layer and the third sub layer are free from p-type and n-type impurities;
• a semiconductor fin overlapping the silicon germanium region, wherein the semiconductor fin comprises germanium;
• and
• a silicon-containing cap adjoining a top surface and sidewalls of the semiconductor fin.